资源列表
PICC Modified-Miller Decoder
- Support 106/212/424/848kbps, modified miller code decoder. Si verified.
LCD32
- FPGA驱动3.2寸TFT，IC芯片为ILI9325，触摸屏控制芯片为TSC2046，亲测可用-FPGA drive 3.2-inch TFT, IC chip ILI9325, touch-screen control chip TSC2046, pro-test available
FPGA--Hammingcode
- FPGA实现扩展的海明校验码，本程序用于冗余存储器的校验-Hamming Code
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
vga_verilog
- 在DE1-SOC上运行的verilog HDL代码，可以驱动VGA显示彩条。quartus II 14.0可以直接使用-Verilog HDL code running on DE1-SOC, can drive VGA display color bars. quartus II 14.0 can be used directly
AD9854_VHD
- 基于FPGA的AD9854的调试，可以产生最高120M频率的波形-Debug FPGA-based AD9854 can produce the highest frequency waveform 120M
SDR-SDRM
- 该工程对三星SDR SDRAM（K4S641632）进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等-The project of Samsung SDR SDRAM (K4S641632), read and write, internal engineering points for PLL and reset processing module, SDRAM logic module, S
VGA_controller
- VGA Controller with VHDL
DDR2-verilog
- ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the
ddr3_demo_verilog
- 基于Verilog HDL的ddr3控制器，适用于lattice的ECP3系列-ddr3 controller based on Verilog HDL，used in lattice ECP3 serial FPGA
Ethernet-communication-VHDL-master
- Ethernet communication VHDL you can download it.
DDS
- Verilog实现DDS线性调频，Verilog实现DDS线性调频-Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM