资源列表
Beamforming
- 基于FPGA的波束形成，包括ad转换，数据存储等部分-FPGA-based beamforming, including ad conversion, data storage and other parts. .
CPLD
- 永磁同步电机伺服驱动器中使用的CPLD程序，主要配合DSP进行数据传输。-CPLD program which is used in servo conveter.
example_modbus
- 基于FPGA下的MODBUS通信驱动程序（RS-232通讯程序）-Based on MODBUS communication driver (RS232 communication program) FPGA under
YCbCr2RGB
- RGB 与YCbCr 颜色空间可以相互转化-RGB and YCbCr color space can be transformed into each other
PWM
- 基于FPGA的PWM控制器设计，包含ADC0820模块，按键扫描，PID，PWM控制器等模块，VHDL语言完成，已仿真通过-PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation
Verilog-master
- 包含多个verilog源码，主要是AD7606的官方驱动，备注详细，学习参考。-Comprising a plurality of verilog source code, mainly AD7606 official driver, detailed notes, study reference.
Pmod_tr2
- FPGA pomd 接口演示实验包括蓝牙，gps，液晶显示等-FPGA pomd demonstration experiments interfaces including Bluetooth, gps, LCD, etc.
eda-class-v1.0
- 计算器功能，可加减乘除，可移位,65525以内运算-, calculator functions, addition, subtraction, multiplication, and division can shift, operation within 65525
baseonFPGAclock
- 用verilogHDL语言写的基于FPGA的电子钟。里面包含闹钟、秒表、日历、时间设置等功能，可用LCD显示-verilog language, implemented on the FPGA alarm clock, calendar, time display, stopwatch in one of the electronic clock and calendar. Can be displayed on LCD
AD9826-verilog
- 使用Verilog编写的ad9826的控制模块-the module of ad9826 with verilog
mux_16bit_sign
- 16位有符号和无符号乘法器FPGA源代码-16-bit signed and unsigned multiplier FPGA source code
Vivado-Introduction
- XILINX VIVADO开发使用工具教程-Introduction to the Vivado Design Suite