资源列表
OExp11-OwnMCPU
- 浙江大学计算机组成实验课工程代码，多周期CPU设计控制器实现。-Multi-cycle CPU design of the controller.
hdmi_demo
- hdmi 视频编解码输入输出模块，verilog实现-hdmi encoder and decoder in verilog.
IP
- USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
fsmc_fpga
- FPGA和STM32通讯的例子，keil和quartus软件程序-Examples of FPGA and STM32 communications, keil and quartus software program
svpwm
- SVPWM verilog source code
BC2
- 芯片驱动控制程序，实现BC模式 B61580 1553B-B61580 1553B
RT.v
- B61580 1553B RT模式配置,芯片驱动控制程序-B61580 1553B RT
RT-ADDRESS
- 芯片驱动控制程序 61580 1553b rt-61580 1553b rt
RT-DATA
- 61580 1553b rt 芯片驱动程序 地址-61580 1553b rt address
HDMI_FPGA
- 该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植-The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted
dma_bridge_verilog
- DMA控制模块的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-DMA control module design reference, for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
AGV_1
- 修改了黑金源码的串口通讯问题，是AGV的通讯部分程序-Modify the source of black gold serial communication problem, communication is part of the program AGV