资源列表
dadishu_v1
- VHDL实现简单打地鼠游戏机，北邮数电实验-VHDL simple playing hamster games, BUPT number of electric experiment
sswcsz3
- VHDL实现猜数字游戏，北邮数电实验，功能齐全，有伪随机-VHDL realization guessing game, BUPT number of electric experiment
pinlvji
- 频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C-Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digita
ZX_SOPC0
- 基于FPGA的DDS信号源设计 1.输出信号为正弦波、三角波及脉冲 2.信号幅度可调,范围：1V~5V 3.调幅步长：10mV 4.信号频率为低频：10HZ~1MHZ 5.频率调节步长10HZ~100HZ频段为1HZ,100HZ~1kHZ频段为10HZ,1KHZ~1MHZ频段为100HZ 6.频率调节方式通过键盘输入 7.运用LCD显示信号的类型、幅度、调频步长、调幅步长-DDS source FPGA-based design 1. The output sig
fft1024-verilogCODE
- fft 1024点verilog代码,适用于基-4的FFT算法描述，使用quartus，modelsim，-fftpoint 1024 verilog code
renyi
- 基于FPGA的任意波形发生器的设计源程序-Achieve arbitrary waveform generation
QPSK
- modelsim环境下QPSK解调电路的仿真-modelsim simulation environment under QPSK demodulation circuit
SPWM-pulse-control-program
- fpga程序，用于逆变器的SPWM控制，有保护程序，包括脉冲闭锁保护，有注释，非常好用-fpga program for PWM inverter control, there are savers, including pulse lockout protection, notes, very easy to use
sd_ctrl
- Verilog写的基于FPGA的SD卡的读写程序，能够读出SD卡中存储的数据-Write Verilog FPGA-based SD card reader program, it is possible to read out the data stored in the SD card
CLK_DIV_IP_packager
- Vivado IP packager的实例。Vivado版本2014.2，使用Verilog语言对一个分频程序打包。-Examples of Vivado IP packager. Vivado version 2014.2, using the Verilog language for a division of the program package.
verilog
- 数字信号处理的FPGA实现(第3版) verilog源码-FPGA digital signal processing (3rd Edition) verilog source
IQ_SIGNAL_GENERATION_CODE
- IQ信号发生器_好用_测试正确,项目已经使用-IQ signal generator _ with _ test correctly