资源列表
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
flash_test
- 使用Verilog HDL语言驱动FPGA读写flash(FPGA read and write flash)
数字信号处理的FPGA实现-第三版-verilog源程序
- 数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
实验11 电容触摸按键实验
- 电容触摸屏实验 采用触摸屏 基于stm32 实现实时控制(Capacitive touch screen experiment, touch screen, real-time control based on stm32)
实验12 OLED显示实验
- OLED显示实验，采用实时显示，基于stm32单片机(OLED display experiment, using real-time display, based on STM32 microcontroller)
四通道DDS信号发生器
- 四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)
jt136
- Filtering summation way broadband beamforming, Power System Transient Stability Program, can be transient stability, Monte Carlo simulation method of calculating the American option price and basic descr iption.
CCD_drive
- TCD1304 CCD 驱动 AD转 USB2.0传输(This code based on verilog language, worked on EP1C3T144 FPGA chip, developed on Quartus II 12.0 . The ccd's data transformed by USB2.0 after amplified and AD confromed.)
Verilog数字系统设计教程(第2版)
- 主要针对用VHDL语言开发FPGA编程学习资料，简单实用。(Mainly for the use of VHDL language development FPGA programming learning materials, simple and practical.)
Vivado 2016.1 安装流程
- Vivado是 Xilinx新一代针对7系列及后续 系列及后续 FPGA 的开发平台。 Vivado 2016.1是官方首个支持 是官方首个支持 win10的版本。(Vivado is the new generation of Xilinx for the 7 and subsequent series and subsequent FPGA development platform. Vivado 2016.1 is the official first support, is the of
SV_AVMM_DMA_DDR3_128M
- altera公司avmm借口pcie dma设计实例，在实际工程中应用成功(Altera avmm, Inc., PCIe DMA design example, applied successfully in actual engineering)