资源列表
traffic_light
- 设计一个简单的交通灯控制器,交通灯显示用实验箱的交通灯模块来显示。系统时钟选择时钟模块的1Hz时钟,黄灯闪烁时钟要求为1Hz,红灯15s,黄灯5s,绿灯15s。系统中用CPU板上的复位按键进行复位。(Design a simple traffic light controller, traffic lights show the use of the experimental box traffic lights module to display. System clock select cl
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入,再按列读出;解交织过程是数据先按列写入,再按行读出。其特点是结构简单,但数据延时时间长,而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
HanoiTower
- 使用Verilog HDL 以及VHDL语言,运用FPGA中的VGA显示原理以及键盘控制原理,开发汉诺塔简易游戏(The use of Verilog HDL and VHDL language, the use of FPGA in the VGA display principle and keyboard control principle, the development of Hanoi simple game)
digital_clock
- vivado 学习资料 数字时钟设计 新建工程后导入相关文件(source)(digital clock Vivado learning materials Digital clock design, new construction, import related documents (source))
夏宇闻Verilog经典教程
- 夏宇闻经典教程,里边有几个章节讲的比较好,初学者可以参考(Xia Yuwen classic tutorial, there are a few chapters about the better, beginners can refer to)
FPGA设计高级篇(Xilinx版)
- FPGA设计的高级篇,xilinx出品,适合已经入门想要进阶的学习(FPGA design advanced article, Xilinx produced, suitable for already started, want advanced learning)
axi3_axi4_perfect
- 介绍AMBA,axi3 与 axi4的一些基本知识,并详细介绍了传输特性(Introduction to AMBA. Some features between axi3 and axi4 and transfer features)
code
- 使用HLS实现的能进行手写识别的CNN网络,使用的是MNIST数据集(Realize CNN network using HLS tool)
Vivado--设计流程指导手册-(含安装流程与仿真)
- vivado设计流程指导文件,里面包含有软件安装流程以及仿真流程(Vivado design flow guidance document, which contains software installation process and simulation process)
ADS7946
- 关于ADC7946的驱动,使用Verilog语言写的。亲测没有任何问题(The driver module about the ADC7946)
f32c-master
- FPGArduino源码,f32c:VHDL的MIPS和RISC-V指令集实现(FPGArduino source code, f32c:VHDL MIPS and RISC-V instruction set implementation)
定点乘法器设计
- 讲解FPGA逻辑设计的乘法器设计方法,优化逻辑资源(Explain the multiplier design method of FPGA logic design and optimize logic resource)