资源列表
sw_debounce
- 按键消抖，更改计数值可随意调节按键消抖的时间。(Button to shake down, change the value of the meter, you can adjust the button to shake time.)
ARS_SHA_1
- sha-1主控制模块实现了对整个sha-1流程的控制(The SHA-1 main control module realizes the control of the whole SHA-1 process.)
DATA_16QAM_MAP1
- 64QAM星座映射的VERILOG代码zszszs(64QAM constellation mapping VERILOG code)
eetop.cn_cordic_sqrt
- cordic 算法知道正弦和余弦值，求反正切，即角度。(The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.)
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
WhiteBalance_10bit
- 模块功能：通过白平衡消除由光照带来色差（绿雾） 模块输入：亮度增益输出R,G,B三通道像素值（double） 模块输出：白平衡后R,G,B三通道像素值（double）(Module function: to eliminate chromatic aberration (green fog) caused by illumination through white balance. Module input: brightness gain output R, G, B three c
FPGA
- ⑴实验要求基本要求： ①设置一个复位键，按下按键输出电压清零 ②设置两个功能键，控制输出电压以0.2V的步长进行加减。(Pin sets a reset button, press the button to output the voltage reset You set two function keys to control the output voltage by 0.2v step size.)
64位乘法器
- 基于fpga的64位乘法器的实现，基于Verilog(Implementation of 64-bit multiplier based on FPGA)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
PID_Verilog
- PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)
adc_data_receive
- adc器件ads62p49模数转换代码，已在工程中验证可用(ADC device ads62p49 analog-to-digital conversion code has been validated in Engineering)
LFM
- 该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)