资源列表
GF乘法器
- 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)
spi_master_sent
- 在FPGA平台实现SPI传输协议开发，SPI为三总线式。(Implementation of SPI transmission protocol development on FPGA platform)
spiflash
- SPI接口实现，对SPI写，擦出等功能操作，此代码在板子上进行验证过，没有任何问题(SPI interface implementation, write to SPI, wipe out and other functional operations, this code has been verified on the board, there is no problem.)
FIR
- fir滤波器的简单实现，主要用于学习与理解(Simple implementation of the fir filter, mainly for learning and understanding)
UART
- Verilog写的UART 协议。可用于FPGA RS232接口实现。(The UART protocol written by Verilog. It can be used for the implementation of the FPGA RS232 interface.)
新建文本文档
- Verilog编写的按键代码，采用异步串口传输协议，并带有偶校验。(Verilog's key code, asynchronous serial port transmission protocol, and with even check.)
ECC
- 基于汉明码的ECC纠错算法，可纠错1位，供参考(An ECC error correction algorithm based on hamming code can be used for reference)
timer0
- 一个简单的timer，包括定时器，计数器功能模式，非常实用，供参考(A simple timer, including timer, counter function mode, very practical, for reference.)
m60
- 使用verilog实现模六十计数即0-1-2-3-4-5-.......-59-0-1-2的功能。(Use Verilog to realize the function of the mode sixty count, 0-1-2-3-4-5-....-59-0-1-2.)
uart_rx
- UART FPGA串口发送程序，已经调试通过，可以放心使用，谢谢，(Serial transmission program, has been debugged, can be assured to use, thank you)
lab2B(4)LFSR
- 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)