资源列表
Q1.tar
- implementation of basic elecronics components using verilog HDL
Q2.tar
- vereilog design files for beginer
Q3.tar
- hdl using verilog lenguage
Q4-a.tar
- verilog coding beginer level
Q4-b.tar
- beginer level verilog coding
ContadorBCDFinal
- Codigo BCD en lenguaje descr iptivo verilog CINVES
McBSP_8bit_Asyn
- 基于FPGA的Mcbsp通信源码，经过项目实测检验(Mcbsp communication source code based on FPGA,Through the test of the project.)
循环码
- 这是对于循环码编码器的语言，希望对大家有帮助(This is the source code for cyclic code coding, I hope to help everyone)
CPLD文件
- USB_BLASTER的CPLD文件，已编译好，直接烧录即可(USB Blaster for the Altera Corporation)
mac_cache_table
- 实现IP地址和mac地址存储，以及由已知IP地址查询到对应的mac地址(The storage of IP address and MAC address is realized, and the corresponding MAC address is querying from the known IP address.)
FIR
- 采用加法树设计8位乘法器，具有流水线结构7阶FIR滤波器，输入序列信号字长4位表示，并且是无符号数。(An adder tree is used to design the 8 bit multiplier, which has a pipelined 7 order FIR filter. The input sequence signal is 4 bits, and it is an unsigned number.)
crc32
- crc32的实现，循环冗余校验的32bit校验结果。(The implementation of CRC32 is the result of 32bit check of cyclic redundancy check.)