资源列表
SMG
- 实现将BCD码动态扫描显示在数码管上--verilog(The realization of dynamic scanning BCD code displayed on the digital tube --verilog)
AD9854programme
- 利用FPGA启动AD9854进行扫频,用于频率特性测试仪。并通过Wify模块发送数据(FPGA is used to start AD9854 for frequency sweep, and is used for frequency characteristic tester. And send data through the Wify module)
sfifo
- fifo 控制器,也是转载的,主要是为了积分(A fifo controller verilog descr iption.)
IICPractice
- 在FPGA上实现IIC总线发送接收的程序(The program of sending and receiving IIC bus on FPGA)
project2
- 基于Verilog在quartus平台上搭建的串口通信模型,适用于初学者。本实验所用RXD的波特率为9600,TXD波特率为9600×16,1位起始位,8位数据位(ASCII码),1位停止位,无奇偶校检位。接收数据时,至少连续采样8个周期都是“0”后,才认定为起始位,之后每隔16个周期取一次数据。(Verilog based on the quartus platform to build a serial communication model, suitable for beginners.
shiftreg44
- 一个用来构成缓存原件的基础 计数器和移位寄存器(Base counter and shift register for a cache primitive)
src
- Spartan-3E. Working VHDL code for amplifier LTC6912, adc LTC1407A-1, dac LTC2624. Archive includes vhdl files and ucf file with comments. Create new project add files and it will be to work.
FiniteStateMachine
- 一个可以识别正则表达式的状态机,采用了多种Case描述,方便修改(A finite state machine designed for identifying expression patterns)
n-bit adder
- n-bit optimized adder using VHDL
1602 clock
- 简单显示时间功能 时-分-秒 以及 文字(Simple display time function - minute seconds and text)
Linux_rev3.1
- Altera FPGA PCIe驱动,在实际项目中使用(Altera FPGA PCIe driver, used in the actual project)
ethernet_loopback
- 通过FPGA驱动千兆以太网口,完成SPARTAN6上的UDP数据包闭环测试,即通过网口发送数据包到FPGA,FPGA内部将接收到的数据返回到PC机,建议测试之前添加ARP静态绑定,FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到,发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the ne