资源列表
Ethernet
- 简易以太网测试仪包含fifo缓冲模块，crc校验模块，检测和检测模块等(Simplified Ethernet Tester: including fifo modular, crc modular, check modular etc.)
vote
- 设计一个100人投票器，超过70人算通过，用verilog语言设计(Design a 100 person voter, more than 70 people passed, using Verilog language design)
mul8
- 用verilog设计了一个两个8位二进制数的乘法器(A multiplier of two 8 bit binary numbers is designed with Verilog)
clock
- 用verilog语言设计了一个数字钟，可以在板子上运行成功(A digital clock is designed with Verilog language, and it can run successfully on board)
jishi
- 用verilog语言设计了一个万年历，包括闰年判断，仿真正确(A calendar is designed with Verilog language, including leap year judgment, simulation is correct)
fenpin
- 用verilog语言设计了一个分频器，晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)
fifo
- fifo in qurtuas using verilog
vga256display
- 这是VGA256色输出的verilog程序(vga 256 colors dispaly module)
04_led_test
- 完整的跑马灯的FPGA代码，芯片为xilinx的S6(run led FPGA code , based on S6 of xilinx)
05_key_test
- 按键的使用FPGA代码控制，包括去抖动等；(Button using FPGA code control, including jitter and so on;)
06_pll_test
- 锁相环IP核的使用，包括详细的配置，适合学习使用；(The use of PLL IP core, including detailed configuration, suitable for learning to use;)
07_uart_test
- uart通信协议的Verilog编码实现，以及完整的测试文件。(UART communication protocol Verilog encoding implementation, as well as a complete test file.)