资源列表
10_rom_test
- rom ip核的配置，以及测试文件，适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
EGO1快速上手指南v1224
- EGO1快速上手指南，适用于新手进行学习(EGO1 Quick Start Guide)
Vedic_Vhdl
- implementation of vedic mulitplier on nexys3 fpga board
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man
adc
- 使用verilog 硬件描述语言编写的ad采样模块，希望对大家有用。(Using Verilog hardware descr iption language written in AD sampling module, I hope useful for everyone)
Verilog_Ip_PLL
- 使用verilog 硬件描述语言编写的PLL调用程序，希望对大家有帮助！(Using Verilog hardware descr iption language written in the PLL call program, I hope to help you!)
A4_Key1
- 使用verilog 硬件描述语言编写的按键电路模块，希望对大家有帮助！(Using Verilog hardware descr iption language to write the key circuit module, I hope to help you!)
A4_Beep
- 使用verilog 硬件描述语言编写的蜂鸣器电路模块，希望对大家有帮助！(Using Verilog hardware descr iption language to write the key circuit module, I hope to help you!)
project_ALU
- 4-bit ALU for adding and subtracting 4 bit numbers. It displays the output on the sevensegment display
add_1p
- 用于FPGA的加法器实现程序，采用Verilog语言编写(Adder implementation program for FPGA)
add_2p
- 用于FPGA的加法器实现程序，采用Verilog语言编写，使用了两级流水线方法(Adder implementation program for FPGA)
add_3p
- 用于FPGA的加法器实现程序，采用Verilog语言编写，使用三级流水线方法(Adder implementation program for FPGA)