资源列表
状态机
- 本代码跟据状态转移图，通过verilog实现了一个有限状态机。(This code implements a finite state machine with the state transition graph through verilog.)
遥控器编码电路
- 该代码根据时序图，采用verilog代码实现了遥控器编码电路的功能。(The code according to the timing diagram, using Verilog code to achieve the function of the encoding circuit of the remote controller.)
遥控器接收解码电路
- 设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial
dds1
- dds输出一个正弦波，通过修改频率控制字来控制频率(DDS outputs a sine wave to control frequency by modifying the frequency control word)
PLX_SDK_v7_11_Final_2014-03-04
- PLX公司最新PCI开发工具包 2014-03-04最新版本(PLX Latest PCI Development Kit 2014-03-04 The latest version)
vivado_license_2016.4
- vivado 2016.4 license
dot_matrix
- 数码管从一到九 信息二维数组类型的分表现的装置 本店的数量越多，高分辨率支持(The digital tube is from one to nine)
spi_master
- spi通信主从模式 可以设置速率/工作模式(Master slave mode of SPI communication)
code_cover_on_black_level_test_project1
- 视频处理的黑电平校正模块的代码覆盖率测试所用的TB(The TB for the code coverage test of the video processing black level correction module)
工作簿1
- 主要关于合肥工业大学计算机方面的知识，有数据结构，计算机组成原理，java，面向对象，(Just hole teacher talk, so that six new development of the party, you find a time, with the volunteer book, together to find the blue Secretary talk, @ Wang Kuo, you're responsible for this thing, a common
cpu_vhdl_vivado
- 一个在fpga平台上的基本cpu的demo...........(A basic CPU demo on the FPGA platform...)
oneMHZ
- VHDL语言编写的20Mhz分频器，时间为1秒(20Mhz frequency divider)