资源列表
shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
VHDL05
- ALU算术逻辑运算模块设计代码。内容简单。是个不错的代码，学习的人可以下载参阅。-ALU arithmetic logic operations module design code. Simple. Is not a bad code, people can download the study refer to.
Marquee-VHDL
- 一个用硬件描述语言VHDL进行编写的跑马灯程序，通过改动数据可控只灯亮的顺序-A hardware descr iption language VHDL program for the preparation of the marquee, change the data controlled by the order of only light
dds2
- 同样逻辑分析仪中部分硬件描述语言VHDL做的DDS模块，-The same part of the logic analyzer in VHDL hardware descr iption language modules do DDS,
asagi_yukari_sayici_entity
- vhdl up down counter, entity,vhdl, good source code
add83coder
- 实现加法器和83译码器的功能！写的很好的verilog程序！-Adder and 83 to achieve the function of the decoder! Verilog to write a good program!
mux41
- 实现VHDL语言4选1通道，在FPGA下实现。-VHDL language to achieve 4 to 1 channel, in the FPGA to achieve.
8lu
- 8路彩灯控制器，运用VHDL语言，EDA技术-8 lantern lantern controller 8 controller 8 lantern controller
fasong
- 发送正交码文件。可根据此文件设置任意长度和比重的正交码。-Send orthogonal code files. Can be set to any length and proportion of orthogonal code based on this document.
VGAS
- vga for fpga vhdl so enjoy learn about vhdl
pwm
- VHDL, quartet 2 , FPGA, cyclone II, controllen PWM brightness
mealy_0011_detector
- Key detector a given bit stream-Key detector a given bit stream