资源列表
counterfour
- verilog code for counter four
VHDL
- DDS产生正弦波（VHDL语言）用DDS产生3MHZ的正弦波,VHDL控制语言-DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
contador_0a7
- contador de 0 a 7 que se reinicia
Stepper_motor_fsm
- stepper motor fsm is the fsm for stepper motor. It indicates the states of stepper motor.
fulladder
- vhdl code for full adder program using libero software.
RAMexio
- verilog 语言的，PWM测试 梯形图速度控制程序新鲜的-verilog language, PWM speed control test procedures fresh Ladder
ram
- a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
fsm_mo10counter
- 模十计数器，状态机，用状态机控制计数器，00为保持，01为加1计数，02为+2计数-module10 counter
control
- vhdl控制源程序，调试通过vhdl source code control-vhdl source code control
FPGAandAT89S52
- 实现单片机与ＦＰＧＡ通信、传输数据、主要用于做ＦＰＧＡ信号发生器-FPGA and AT89SS52
lfsr_top
- LP LFSR for low power test pattern generation_V
ext
- 32位数据扩展，可以将16位的数据扩展为32位，分为算数扩展和逻辑扩展。-32 data extensions that can be extended to 16-bit data 32, into extended arithmetic and logical extension.