资源列表
树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
DG408
- FPGA对模拟开关DG408的控制程序，实现不同需求的情况下，模拟通道的转化。-FPGA on the DG408 analog switch control procedures, to achieve the different needs of the circumstances, the conversion of analog channels.
airconditioner
- 中央空调的控制，3级控制系统，这个是中间控制的vhdl源代码-Central air-conditioning control, 3 control system, this is the middle of the control of vhdl source code
CNT4
- 4位二进制加法计数器的两种不同VHDL的描述,与比较。-4-bit binary addition of two different counter VHDL descr iption, and more.
ent_mux
- ethernetmux for 34.5 mbps agregate
Cuantificador
- Cuantificador con 3 bits (Niveles graduables)
adder4
- adder 4 bit use component architecture in VHDL
autosell
- 自动售货机程序，以Verilog三段式描述方法描述有限状态机FSM，编译及输出正常-Vending machine program, describe the method described in Verilog three-finite state machine FSM, compile and output normal
digi_clk
- Digital watch in VHDL.
ASK_modulation_code
- ASK调制VHDL程序，好用，已测试通过-ASK modulation VHDL program, easy to use, has been tested
VHDL 1602
- VHDL的1602代码，基于FPGA的1602液晶代码
jiecheng
- 利用Verilog语言中的函数调用实现阶乘运算的功能-Function calls use Verilog language implementation of the factorial function computing