资源列表
ad73311
- AD73311芯片的控制和数据程序，用于控制音频AD芯片。(AD73311 chip control and data program)
ambo2000
- AMBE2000芯片的控制，和编码方式控制，码率的控制，成熟的可配置的控制模块。(AMBE2000 chip control and coding control, rate control, mature and configurable control module.)
i2c_slave
- I2C从机模块，支持多种I2C模式，稳定成熟，方便使用。(I2C slave module supports multiple I2C modes, which is stable, mature and convenient to use.)
myclock
- implement a 12-hour clock(This is a 12-hour digital clock, hout designates the hour, mout designates the minute, sout designates the second, and pout designates morning or afternoon. For example, if current time is 3:08:12 pm, then hout = 3, mout = 8
DE2_synthesizer
- 基于DE2FPGA开发板的多功能音乐合成器研究实现与综合(based on DE2 FPGA 2C35 development board design music synthesizer string base)
led_test
- 流水灯例程，是FPGA的入手级程序，初步了解FPGA的时序(The water lamp routine is the start procedure of FPGA, and initially understands the timing of FPGA.)
at7_ex01
- 8个LED执行流水灯。流水灯依次循环点亮。基于vivado平台编写的Verilog代码(The 8 LED executes the flow light. The flow light is turned on and out in turn. Verilog code based on vivado platform)
at7_ex03
- 使用FPGA内部的PLL产生时钟，计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
at7_ex04
- 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at rando
at7_ex05
- 实现PC端通过UART发送数据到FPGA，FPGA将所接收到的数据同样是通过UART原本不动的发回给PC端。(The PC terminal sends data to FPGA through UART. FPGA sends the received data back to the PC end by UART.)
DLL_clock_generator
- DLL is useful for the ug and pg sdents tu
Aircon
- VHDL code for air con