资源列表
扰码器Verilog
- 实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)
src
- 基于AXI 总线的可配置脉冲计数器，可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)
my_led_ip
- 四通道axi LED灯控制器，用于嵌入式系统中的一些功能指示(The four channel Axi LED lamp controller is used for some function instructions in the embedded system)
zcu102_exp_1
- 给予Xilinx系列zcu102开发板，完成了一个基本的project，实现了PS 端对PL 端的控制，并在PL端自己生成IP，是初学者很好的学习模板。(Xilinx series zcu102 development board, completed a basic project, the PS end to the PL control, and the PL end of the generation of IP, is a good learning template for begi
bpi
- bpi相关设置 vhdl中的bpi设置及相关介绍(in bpi using in fpga introduciton of bpi and using of fpga)
LMS_filter_Altera
- 2017电子竞赛e题软件部分,fpga实现(lms adaptive filter undergraduate electronic design contest)
intel fpga user manual
- quartus 官方使用手册，intelFPGA,原ALTERAFPGA(The official manual,the Intel fpga user manual)
try
- 利用xilinx公司开发的vivado平台中的IP核-加法器，实现加法(The addition of IP core adder to the vivado platform developed by Xilinx is applied.)
test
- 利用xilinx公司开发的vivado平台中的IP核-rom，实现存储(Using IP core -rom in vivado platform developed by Xilinx, storage is implemented.)
oo
- 利用xilinx公司开发的vivado平台，实现下变频功能(We use the vivado platform developed by Xilinx to realize the down conversion function.)
demo
- 利用xilinx公司开发的vivado平台，实现调用romIP核的功能(Using the vivado platform developed by Xilinx, the function of calling romIP core is implemented.)
one_1bit
- 利用xilinx公司开发的vivado平台，实现调用1bitpwm信号实现下变频的功能(Using the vivado platform developed by Xilinx, we can realize the function of calling down the 1bitpwm signal to realize the down conversion.)