资源列表
adc_data_receive
- adc器件ads62p49模数转换代码，已在工程中验证可用(ADC device ads62p49 analog-to-digital conversion code has been validated in Engineering)
RS232
- 串口收发代码，可设置速率，工程中已验证可用(Serial transceiver code, can set the rate, the project has been verified to be available)
LFM
- 该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
UVM验证平台搭建
- 搭建uvm验证平台,通用验证平台结构和搭建流程介绍(How to build a common UVM verification platform?An easy and useful method is instroduced here.)
apb_timer.tar
- 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the descr
sci_host
- fpga实现高速多路同步串口，接收发送模块(Implementation of high-speed multi-channel synchronous serial port by FPGA)
SPI_ADC
- spi串行输出ADC——AD7989的verilog源代码。(Spi serial output ADC - AD7989 Verilog source code.)
华为经典FPGA设计全套入门技巧
- 华为FPGA设计全套资料，学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)
1553B总线接口技术研究及FPGA实现
- 基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)
SDI_controller
- 项目:用到FPGA驱动GV7600输出SDI信号，输出分辨率1920*1080p，首先，了解GV7600芯片的特性功能，按照bt1120协议传输10位Y，Cb，Cr数据；其次，我的项目中用的是10位通道分时复用传输Y，Cb，Cr数据；配置引脚很重要，当初verilog代码写好了，因为硬件引脚配置错误，导致调试一直不通；同时，sof文件也要一直更新(Based on FPGA to design the drive controller of GV7600)
Zynq 7000嵌入式设计官方教程
- zynq7000 嵌入式设计官方教程，学习嵌入式入门书籍(ZYNQ 7000 embedded design official tutorial, learn embedded introductory books)
05Artix修炼秘籍-Microblaze
- microblaze教程 如何使用microblaze(How to Use Microblaze in Microblaze Tutorial)