资源列表
timeconstraint
- VHDL编程中的时序约束问题,有两个PDF文件,讲的很详细,需要的立刻下载-VHDL programming timing constraints, there are two PDF documents, said very detailed, immediately download the
FSKmodemodulateVHDLprogramme
- FSK调制与解调的vhdl源代码与仿真指导,是word文档打开。-FSK modulation and demodulation of VHDL source code and simulation of the guide is the word document open.
FPGAdesignstudy
- 介绍了FPGA设计全流程 和一些简单的例子-introduced FPGA design the whole process and some simple examples
programggvv
- 洗衣机程序-washing machines procedures
xiaoche
- 用VHDL编程的智能寻迹小车.驱动电机沿黑线运动,转弯的时候有灯显示.可以综合,实际硬件调试通过.是学习VHDL的很好实例-VHDL programming smart tracking.The car. Electric drives along the black line campaign turning the lights are shown. can comprehensive, practical hardware debugging through. learning is a
100vhdl_EXAMPLE
- vhdl的100个例子,希望对大家有用-VHDL of 100 examples, we hope to useful
FIR31
- 设计一个线性相位FIR滤波器(31阶) 输入8位,输出8位,H(n)={1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69,111,128,111,……2,1} H(n)具有对称性。 输入信号范围 [±99,0,0,0, ±70,0,0,0, ±99,0,0,0, ±70,…]
adderN
- N位加法器源代码,通用的,通过xilinx验证,希望对大家有用。-N-bit adder source code, a common, through Xilinx certification, useful for all.
Verilog_intr_c1
- verilog设计进阶,提供大量的设计事例供参考学习-Verilog design provides many examples of the design study for reference
pcirtl
- 用verilog编写的pci——rtl级。-using Verilog prepared by the pci -- rtl level.
automachine
- 自动售货机 l 设计要求: 1.机器有一个投币孔,每次只能投入一枚硬币,但可以连续投入多枚硬币。机器能识别的硬币金额为1元,5角和1角。顾客可选择的饮料价格有1元,1元5角,2元三种。每次只能售出1瓶饮料。 2.购买饮料时先选择饮料价格再投币,当投入的硬币总金额达到或超过饮料价格后,机器发出指示信号并拒收继续投入的硬币。顾客投币后,按动确定键,机器将发出饮料和找零硬币,若所投金额不足,则发出欠资信号指示。在欠资情况下,顾客可以继续投币购买,也可按取消键,机器将退出所投入的全部金额。
car_lamp
- 汽车转向灯控制电路,采用循环点亮三个指示灯指出汽车的转弯方向。-vehicle steering control circuit lights, cycle lights that lit three cars turning direction.