资源列表
vhdlvga
- Language writes with VHDL demonstrates the design on the monitor the source program用VHDL 语言写的在显示器上显示图案的程序-writes with VHDL Language demonstrates th e design on the monitor program with the source VHDL The language was on display in the pictorial proc
Uart2
- uart的VHDL源代码，包括intface.VHD UART_RX_TAB.VHD UART_INT_TB.VHD等-uart VHDL source code, including intface.VHD UART_RX_TAB.VHD UART_INT_TB. Volume etc.
bujindianjiVHDL
- 步进电机定位控制系统VHDL程序与仿真波形．已经在xilinx ISE 8.1上验证．完全正确．-positioning stepper motor control system procedures and VHDL simulation waveform. Xilinx ISE has tested 8.1. Absolutely correct.
sampleVHDL
- 采样等精度测量的VHDL程序．．在xilinx ISE 8.1上验证通过-sampling and other precision measurement of VHDL program. . In xilinx ISE tested through 8.1.
vhdl_clock
- VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends
vhdl_traffic
- 模拟交通灯实验 模拟路口的红黄绿交通灯的变化过程，用LED 灯表示交通灯，并在数码管上显示当 前状态剩余时间。-simulation experiment simulated traffic lights junction of red, yellow, and green traffic lights to the process of change, said LED lights for traffic lights, and the digital tube display th
vhdl_dial
- 拨码开关实验 拨码开关8 位0 1 状态在8 位7 段数码管相应位上显示0 或1。-dial-switch dial-switching experiment 8 0 1 state in seven of the eight corresponding digital control-show or a 0.
1_070116141639
- verilog编程ps2接口设计,基于fpga的设计-verilog ps2 Programming Interface design, the design based fpga
vhdl_led
- 7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7，-seven of the digital control experiments (including two experimental), the digital control of a Test : Dynamic scanning approach to the eight digital control "at the same time" show 0 -7
VHDLnf
- VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency, -- n as long as you want to set the frequency of the numerical breakdown on the
1_061026140305
- 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language. - Based on the FPGA I2C main line simulation, verilog uses the HDL la
chuanbingzhuanhuan
- VHDL代码，仿真通过，变异可以，下载变成文件，但需要修改，串并转换-VHDL code, through simulation, the variation can be downloaded into a document, but need to change, and change series