资源列表
maxII16_cpu
- maxII16_cpu,altera的maxII系列的16位cpu-maxII16_cpu, altera the maxII series of 16 cpu
programing_voltage_current_resources
- 实现电压\\电流的分别输出,可通过按键选择输出通道.-voltage \\ output current, respectively, through the output channel selection buttons.
cf_fft_2048v
- 基于FPGA的2048点FFT的verilog实现的源代码。-FPGA-based 2048-point FFT verilog the source code.
zffsq
- 此文是一个完整的字符发生器的设计及设置,文中有完整的vhdl代码及原理图.-This article is a complete character generator design and installation, a complete text of the code and vhdl diagram.
szzsj
- 本文设计的数字钟具有以下特点: 1、具有时、分、秒计数显示功能,以二十四小时循环计时。 2、具有清零,调节小时,分钟的功能。 3、具有整点报时同时LED灯花样显示的功能。 -This paper describes the design of digital clock with the following characteristics : 1, with time, minutes and seconds count display function, to the 24-h
mnxhjc
- 本实验用DA转换+比较器的方法对外界模拟信号进行检测,同时这种联合装置加上CPLD可以代替低频AD转换器的功能。-this experiment + DA conversion method of comparison to the outside world analog signal detection, while such joint CPLD devices can be replaced with low-frequency AD converter functions.
20074249422318919
- good very good-good good very good
20051122141440
- haha hahahahha hao aho -haha hahahahha hao haoahoaho
VGA_control_verilogHDL
- 基于FPGA的VGA控制器设计。对外支持普通VGA接口,以600×480的分辨率和60Hz扫描率为例。对内支持NIOSII软核接口。
vga.niosII.compent.v
- 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中,用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
DDS_generator
- DDS锯齿波发生器: 开发平台:maxplus+FPGA 功能: 输出X路扫屏锯齿波。频率可用键盘精确控制,设置多个挡位;可水平移动波形;-DDS sawtooth generator : Development Platform : maxplus + FPGA functions : So output X Lu Ping Sawtooth. Keyboard can be used precision frequency control, multiple gear; Mobile
254646
- 数码管动态扫描 vhdl-of dynamic digital scanning vhdl