资源列表
FPGA-CPLD_DesignTool(example3-4)
- FPGA-CPLD_DesignTool,事例程序3-4陆续上传请需要的朋友下载-FPGA-CPLD_DesignTool. 3 -4 examples procedures have requested upload download a friend in need
FPGA-CPLD_DesignTool(5-6)
- FPGA-CPLD_DesignTool(example5-6),需要的朋友可以下载-FPGA-CPLD_DesignTool (example5-6), a friend in need can be downloaded
FPGA-CPLD_DesignTool(7)
- FPGA-CPLD_DesignTool(example7),需要的朋友可以下载-FPGA-CPLD_DesignTool (example7) a friend in need can be downloaded
FPGA-CPLD_DesignTool(8-9-10)
- FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载-FPGA-CPLD_DesignTool (8-9-10) requested the source code to their peers in need Friends Download
CordicverilgHDL
- 实现cordic算法,输入数据为16位,为提高精度,输出为20位。-achieve cordic algorithm, the input data for the 16, to increase accuracy and output 20.
yangwenli
- 计费器设计中速度控制模块、里程计数模块、计费计数模块vhdl源代码-accounting device design speed control module, the mileage counter module, billing module count vhdl source code
control9851
- AD9851的vhdl串行控制程序(9851系统时钟内部指定)-AD9851 vhdl the serial control procedures (9851 designated internal system clock)
GenCrc1
- 并口硬盘标准PATA6的CRC效验码的vhdl代码-Parallel hard disk standard PATA6 the CRC code well-tested code vhdl
std_cf_1c20
- Altera公司开发板1c20 CF卡通用例程(初始化、读、写、测试等)-Altera Corporation development board 1c20 CF cartoon with routines (initialization, reading, writing, testing, etc.)
std_cf_1s40
- Altera公司开发板1s40 CF卡通用例程(初始化、读、写、测试等)-Altera Corporation development board 1s40 CF cartoon with routines (initialization, reading, writing, testing, etc.)
std_cf_2s60_ES
- Altera公司开发板2s60 CF卡通用例程(初始化、读、写、测试等)-Altera Corporation development board 2s60 CF cartoon with routines (initialization, reading, writing, testing, etc.)
CommandResponse
- verilog语言写的sdram控制器—命令响应模块代码,经过测试,逻辑正确,可编译,可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated