资源列表
interpolation_FIR
- Interpolation FIR Design Example for Stratix Devices
fir-vhdl
- 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Descr iption Languages in preparing the FIR digital filter
miaobiao_watch
- 此为秒表程序，具有秒表的一般基本功能，已在MAX+plusII 10.2下编译通过。-stopwatch for this procedure is the general basic stopwatch functions, MAX has been under plusII 10.2 compile.
8251_8055_verilog
- 8251和8055的verilog源码，可进行综合和仿真，是学习SOC的好资料！-8251 and 8055 verilog the source, and integrated simulation, SOC is a good learning information!
adc8888
- 8位的a/d行为模型，可以应用于modelsim等环境下的仿真，不可综合。-eight of the a / d behavior model can be applied to other environments modelsim the simulation, not comprehensive.
sram__
- 静态随机读取存储器行为模型，可以应用于modelsim环境的仿真。-static random acts of reading memory model can be applied to the simulation environment modelsim.
vga_verilog
- 本示例演示了VGA的控制方法，程序配置后可以在CRT上显示中文汉字等信息。-this example demonstrated the VGA control methods, procedures after the distribution of CRT Chinese characters on the show and other information.
PS2keyboard_verilog
- 本实验利用PS2接口实现了与键盘通信，并将键盘的按键编码通过UART接口上传给PC的超级终端，通过超级终端来观察按键编码是否正确。 -experimental use of the PS2 interface with the keyboard communications, and keyboard buttons coding through UART interface to the PC upload the Super Terminal, Super Terminal throug
lcd1621
- 在LCD上显示事先就输入好的字符,可以任意改变的-displayed on the LCD on the admission of prior good character, can be arbitrarily changed by the
JT2MIAN
- 交通灯控制,在A和B方向各用数码管显示剩余的时间.-control traffic lights in the direction of A and B of the digital show the remaining time.
digit_clock
- FPGA设计的时钟！很特别，本人的第一次，还望各位探讨！-FPGA design the clock! Very special, the first time I also hope to explore!
atlrallianxi
- atlral初学练习 vhdl实例联系-atlral novice practice examples linked vhdl