资源列表
24_Timer
- 使用Verilog编写的24位定时器,具有apb 总线接口,可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
Cortex-M1
- Verilog Cortex-M1 source code
VERILOG
- 基础的几个verilog代码实现,讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)
package_control-master
- 从github下载的,能够参考设计AXI4的协议接口(AXI4 Verilog template)
基于basys3的推箱子游戏
- 基于FPGA的游戏实例,开发板为Xilinx的basys3,VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)
08_1_hdmi_output_test
- 基于fpga的hdmi彩条输出实验 , 彩条生成模块加上hdmi编码器,输出TMDS信号接到显示器即可看到彩条。 可以调整输出分辨率(HDMI color bar output experiment based on FPGA The color bar generation module and the HDMI encoder can output the TMDS signal to the display and see the color bar. Adjustable output
master_slave
- AXI4-Lite总线的主从机读写,例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
基于Verilog的基础CPU
- 一个可以进行abs(a+b-c)的CPU,包含仿真代码,完全一步一步进行,具体到细节
1_Carm
- 经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
5_fir_tran
- 经典的verilog语言实现转置型FIR滤波器的代码(Code of Inverted FIR Filter Implemented by Classical Verilog Language)
Hardware-CNN-master
- Convolutional neural network code for fpga
gmsk
- 利用fpga实现gmsk的调制并仿真,全部代码(Fpga implements gmsk)