资源列表
cycle_en_decoder
- 卷积码编码/解码，Verilog语言实现，带仿真程序。-Convolution encoder/decoder, Verilog language, with a simulation program.
fpga_pid
- 在FPGA内使用PID算法反馈控制小车速度和方向，四电机独立-PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors
three_ADF4350_verilog_code
- 该verilog代码实现对三个ADF4350的控制，并附带一个测试程序。-The Verilog code to achieve control of the three ADF4350, with a test program.
K7_1M
- 用Verilog语言实现的以太网驱程，可最多实现8个以太网，外加PHY后，可实现ping操作-Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping
anjian
- 用FPGA实现按键对数码管显示的数字控制，兼有加数、减数功能。使用两个按键及两个数码管。-To achieve key display of the digital tube digital control with FPGA, both the addend, meiotic function. The use of two keys and two digital tube.
emmc_cmd_interface_module
- emmc控制芯片CMD命令线主机接口模块,-emmc control chip CMD command line host interface module
I2C
- FPGA I2C verilog代码，代码有注释。-FPGA I2C slave verilog code,with code remark.
adder_32bits
- 采用“进位选择加法”技术设计32位加法器 Verilog语言编写-32 bit adder
FPGA
- 包括密勒码编解码、循环码编解码、FSK和PSK调制解调-Including Miller encoding and decoding, encoding and decoding cycle, FSK and PSK modulation and demodulation
61EDA_C2701
- 开发环境vhdl FPGA实现的NandFlash控制器（带ECC）文档+源代码-Vhdl FPGA development environment to achieve NandFlash controller (with ECC) document+ source code
SPWM
- 基于FPGA的正弦脉宽调制波vhdl代码，同时输出正弦波与SPWM-Sine pulse width modulation wave VHDL code based on FPGA, at the same time with SPWM output sine wave
Synchronous
- 同步加法计数器，采用D触发器实现的二进制计数器-Synchronous adding counters, D flip-flop implemented using binary counter