资源列表
UART
- Universal async Transmitter Receiver
fast_16bit_counter
- 16位快速计数器,速度达到180MHz,16位快速计数器,速度达到180MHz-16bit counter
IO_controll
- this a controller, mainly for the nexys2 board based around the spartan 3E fpga from xilinx. controlls various outputs and inputs.-this is a controller, mainly for the nexys2 board based around the spartan 3E fpga from xilinx. controlls various outpu
TVR2
- A Modern Stream Cipher - Trivium
leading_8
- This program gives a count of leading zeros in 16 bit number.
shunmaguanxianshidianlu
- 用VHDL语言编写一个八位数码管显示电路，每个数码管的八个段分别连在一起，八个数码管分别由八个选通信号选择。被选通的数码管显示数据，其余关闭-With the VHDL language to write a eight digital tube display circuit, each digital tube eight segments are connected together, the eight digital tube are respectively composed of
ram_sp_ar_sw.v
- this is a verilog source code for Single Port RAM Synchronous Read/Write.
vhdl_codes
- D-flip flop vhdl implement code
AD
- 有限状态机的设计——0809 A/D转换实验-VHDL for ADC0809
LED
- 流水灯设计原则以及源代码的编写,主要在器件上实现CPLD-Flowing water light design principle and the writing of the source code, mainly for the CPLD device
TCD1001P-driver-Verilog
- 东芝线阵CCD-TCD1001P驱动程序源代码，verilog编写-Toshiba linear CCD-TCD1001P driver source code, Verilog write
compare
- 用verilog实现文件输入的比较器，如果同一时间输入的数据相同则输出高电平，否则输出低电平，达到比对的效果。-Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.