资源列表
tetris-FPGA
- 一款简单的俄罗斯方块游戏，用Verilog编写源码，方便大家学习-A simple tetris game, written in Verilog source, convenient for everybody to learn
KD1024x600
- 使用FPGA驱动TFT屏。此程序为RGB24位驱动,不含SPI接口。-Use the FPGA screen driver TFT. This procedure for the RGB24 bit drive, not including the SPI interface.
xuliejianceqi
- 序列检测器00101，包括源代码，testbench，ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
SDH
- SDH vhdl实现-SDH VHDL
quartus-II
- 用Quartus II实现答辩计时器设置，大致功能有时间显示，倒计时提醒，暂停键等。-Quartus II realized by the respondent timer settings, roughly the time display function, countdown reminder, the pause button and so on.
RS422_UART
- RS422 串口通讯 （包括 testbench，虚拟RAM，数据收发，波特率生成，数据接收抗干扰）-RS422 UART testbench BaudGen
Norflash
- 用verilog hdl写的Norflash控制器，可实现单字节读写，扇区擦除。-Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.
RLS.v
- 用verilog实现的一个2抽头RLS自适应滤波器的代码-A realization with verilog HDL code of a two-tap RLS adaprive fliter
MultHalfBand
- 多级半带滤波器的FPGA实现,采用6级滤波器实现的采样频率由3200Hz降为50Hz的抽取系统，前5级为半带滤波器,最后一级为普通FIR滤波器-Multi-level half-band filter FPGA, using six filters for sampling frequencies 50Hz down to 3200Hz extraction system for the front five and a half-band filter, the last stage of
ug947-vivado-partial-reconfiguration-tutorial(1).
- tcl partial reconfig synthesis code
AD5300
- FPGA外部AD部分代码，FPGA芯片采用xilinx sptan3e 可以实现AD的采集-The FPGA external AD code, the FPGA chip using xilinx sptan3e can realize the collection of the AD
SPI
- FPGA SPI部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA的SPI的通信,用来控制外部74hc595-FPGA SPI part of the code, the FPGA chip using xilinx sptan3e can realize SPI communication, FPGA is used to control the external 74hc595 are needed