资源列表
shift_reg_sp
- serial to parrallel shift register
EDA3
- 该程序是一个带记数使能，异步复位，带进位输出的增一 二十进制记数器，记数结果由共阴极七段数码管显示-The program is a band count enable, asynchronous reset, into digital output by 12 decimal counter, counting the results from the common cathode seven-segment LED display
BUFG_CLK2X_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
mul
- 可实现输入的2个一位十进制数的乘法运算。要求：输入提供十个数字键，先转化为8421码，再运算，输入的数据和输出结果都要以七段显示译码器显示出来（仿真波形）。输入模块、运算模块、数据转换模块要求用不同的模块分别实现。-Can be one of the input of two decimal multiplication. Requirements: Enter the ten numeric keys provided, the first transformed into 8,421 yar
DECODE_PRIORITY
- 优先译码器verilog，8输入3输出，用verilog编写的源码-This is how to prepare encode, I think is very classic. Worth a visit
abc
- 总线控制，用于嵌入式系统也fpga通信，主要用用于的产品是光时域反射仪-The bus control for embedded systems fpga communication products, mainly used for optical time domain reflectometer
ca_code
- nco的产生原理的相关代码；软件无线电、直接数据频 率合成器（DDS，Direct digital synthesizer）、快速傅立叶变换（FFT，Fast Fourier Transform） 等的重要组成部分，同时也是决定其性能的主要因素之一，用于产生可控的正弦波或余弦波。随着芯片集成度的提高、在信号 处理、数字通信领域、调制解调、变频调速、制导控制、电力电子等方面得到越来越广泛的应用-nco the generation principle of the relevant code s
fulladder.v
- 自己写的full adder的verilog代码，请大家下载。如果有问题请评论给我-Write your own full adder verilog code, please download. If you have questions, please give me a comment
barrelshifter32
- 32位桶形移位器，可以实现算数右移、逻辑右移、算术左移和逻辑左移。-32-bit barrel shifter, can achieve an arithmetic right shift, logical shift right, left arithmetic and logical left.
finite-state-machine
- 有限状态机，程序基本框架，需用户自行添加状态转换条件等-finite state machine
PLB_MG
- PLB Macrogate in VHDL
lfsrupdwn.v
- This left shift register.-This is left shift register.