资源列表
shuzishizhong
- 用verilog语言写的数字时钟程序 芯片是EP2C8Q208C8-Verilog language used to write the digital clock program chip EP2C8Q208C8
x86
- 一个开源的X86处理器的Verilog代码-Verilog source code for x86
interleaver
- 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
SERDES
- 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
fec_encode
- 一个有关RS（255，239）编码的代码，这是一个项目工程上的，用时可以自己修改下。-A related RS (255,239) code code, which is a project engineering, can make changes to it with the next.
dac8552
- 使用Verilog HDL语言编写的实现DAC8552的时序程序，单片机总线与CPLD/FPGA通信，单片机负责控制送数实现功能。-Use Verilog HDL language DAC8552 realization of temporal procedures, SCM bus and CPLD/FPGA communication, SCM control to send several functions.
DDC_Ver1.0
- 数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值-Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code
FPGA-DSP
- vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信-vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP
communications_2
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或），crc解码，数据串行输出。 -Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), no
LIP4210CORE_SDIO
- SDIO Verilog Sourcw code
SerDes-Architectures-and-Applications
- 关于lvds四种串行解串器的架构和应用的详细介绍和讨论，非常适合初学者使用-About lvds of four serial SerDes architecture and applications presented and discussed in detail, ideal for beginners
dsp
- dsp2812板子的所有资料，包括pcb板子和sch板子！-dsp2812 board of all information, including sch pcb board and the board!