资源列表
songer
- VHDL语言实现设计音乐功能模块的源代码，-VHDL language implementation design of musical function module source code,
data_rom
- 正弦波信号发生器 正弦波信号发生器 -sine wave signal generator sine wave signal generator
clk_div_n
- 时钟任意分频模块，输入为主时钟和分频数，输出为主时钟/分频数。-Clock divider
VerilogCode_7_segment_decoder
- Verilog Code for seven segment decoder for the code to be implemented on Altera DE2 board
IIC_RD
- 基于FPGA板得方针操作 在数码管显示24c02值-Approach based on FPGA board was operating in the digital display 24c02 value
5
- 七段字符显示器逻辑功能的VHDL语言程序，本程序采用IF语句形式-VHDL language program of the seven-segment character display logic functions
pwm
- PIC16F4011实现PWM波形，可以直接用-PIC16F4011 PWM
Frecdiv
- Frecuency divisor with 3 bits of variable.
lfm_ambi
- 线性调频信号chirp lfm信号的模糊函数 matlab编写 -Linear frequency modulated signal ambiguity function of the signal of the chirp lfm Matlab prepared
ARM_shift_32bits
- ARM架构下的32位桶形移位器的verilog源码-32-bit barrel shifter verilog ARM architecture of the source
crc
- 基于verilog的CRC算法-CRC algorithm based on verilog.
time60
- 一个占用资源很少的时钟产生Verilog代码，值得借鉴-A small footprint clock generator Verilog code, is worth learning