资源列表
picoblaze07.3.20
- verilog HDL picoblaze07.3.20
pljfpja
- 频率计的fpja部分程序,,,用高精度测频法实现。。。能测1、、1M-frequency of fpja some of the procedures, and using high precision frequency measurement method to achieve. . . Can be measured one, and 1M
pio_top
- 这个verilog代码是一个输入输出经典的例子。大家一起参考。-the verilog code input and output is a classic example. Together reference.
ClockOut
- 通过VERILOG编程,实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
DDS_Power
- FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波,方波,三角波,斜波,以及四种波形的任意两种的叠加,以及四种波形的叠加;通过控制频率控制字C的大小,以控制输出波形频率,实现1Hz的微调;通过地址变换实现波形相位256级可调;通过DAC0832使波形幅值256级可调;通过FPGA内部RAM实现波形存储回放;并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table thr
NumClock
- 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括:基本功能——以数字形式显示时、分、秒的时间,小时计数器为同步24进制,可手动校时、校分;扩展功能——仿广播电台正点报时,任意时刻闹钟(选做),自动报整点时数(选做);其它扩展功能——显示年月日(能处理
02_SynthesizableMATLAB
- Lab 2 – Synthesizable MATLAB This lab exercise will explore the effects that different MATLAB coding styles have on hardware. The lab has two parts, each of which begins with a short introduction. This lab exercise is based on the simple MATLAB FIR
cabine
- 3层电梯的控制,利用vhdl写的。运行于maxplus-three-storey elevator control, the use of vhdl writes. Running maxplus
canbus_vhdl
- 使用方法: 1.拷贝到硬盘,用ISE打开工程文件即可。-Use : 1. Copy to the hard drive, use ISE project documents can be opened.
usb_2
- usb2的FPGA实现,verilog语句-usb2 FPGA, verilog statement
16B20B
- 16B20B编码转换,用于高速的串型接口-16B20B encoding conversion for the high-speed serial interface -
fcout
- 频率计源代码,性能很好,verilog写的,顶层原理图,底层语言写的,效果很好,开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus