资源列表
dpsk_m_fpga
- 能够进行FPGA实现的DQPSK仿真程序！ -The DQPSK simulation program which can be implemented in FPGA.
div
- 32位整数阵列除法器，verilog代码编写，性能高效。-32-bit integer array divider, verilog coding, performance and efficient.
SHIZHONG
- 这个是我自己做的一个电子时钟，用4位数码管，合泰单片机-This is my own doing an electronic clock, with four digital control, microcontroller Hetai
EDA
- 彩灯控制系统及状态机程序设计，主要源程序及仿真图、状态图-Lights control system and state machines
sram_verilog
- verilog 源代码，非常简单的一种SRAM的可综合的写法，适合新手学习之用。-verilog source code，simply implementation of SRAM with synthesisable coding-sytle， special for the beginners.
SMY01-02
- SMY01 02信号发生器使用手册说明,对于开发人员来说很有好的
TSMC130
- 本文档提供重要信息，并通知有关此版本的PDK的。谁想要或计划使用的PDK的用户，应先阅读整份文件。-This document gives important information and notice regarding this release of PDK. Users who want or plan to use this PDK should read the entire document first.
new_bord_TX_10bitX2_2_5G
- Xilinx VirtexII-pro 的开发板工程文件，它是在ISE开发环境中实现的。连接有RAM、串口、LED灯、Camera-link接口等，实现的从工业相机到光缆的转换。-xilinx virtex2-pro project,camera-link
Uart
- fpga verilog语言，写的串口通讯，经测试完全没有问题-fpga verilog uart communication
spi-uart
- 这个程序是C8051F30x设备通过 spi 通讯然后从串口发送的例程 具有 spi 跟串口的初始化操作-This program sets up the GPIO pins on the C8051F30x device for the correct functionality, then uses the SPI_Transfer function to send and receiveinformation through the SPI pins. As information
AssignmentP7
- 1. Design a VHDL model for a 4-bit up-and-down synchronous binary counter with carry and borrow signs using FSM. Verification of this design is especially appreciated.
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)