资源列表
vhdl
- 实现8421BCD码转换为5421BCD码求和运算-Achieve 8421BCD code into 5421BCD code summations
TEST3
- T0发出周期为2S的脉冲，T1做计数器计数，并动态扫描显示计数脉冲数。-Given period of 2S T0 pulse, T1 do counter, and dynamic scanning display count pulses.
juzhenjianpan
- 4*4矩阵键盘，并在8位数码管上显示按键值-4* 4 matrix keyboard, and 8-bit digital value displayed on the button
if-receiver
- 中频数字接收机设计与实现 对中频数字接收机方案的可行性作了分析，并通过系统仿真工具SystemView对A／D，数字下变频(DDC)及AM、FM等调制信号的软件解调作了仿真。-Design and implementation of a digital intermediate frequency receiver
Altera-Cyclone-III
- Altera Cyclone III Component library
EP2C8Q_Nios_RTC
- 在2.4寸TFT屏上显示时间，主要用NIOS控制。-Display time on 2.4-TFT screen.use nios to control the program
VHDL-1602
- 程序基于FPGA芯片，使用VHDL语言编写，实现驱动LCD1602A显示的功能。-FPGA-based program, using the VHDL language, to achieve drive LCD1602A display functions
mlt
- 基于FPGA 的乘法器 时间两个数相乘，并在数码管显示-Based on the FPGA multiplier time multiplied by the number two, and in digital tube display
lcd12864_test
- 基于nios II核，实现对LCD12864的操作，显示基本汉字等字符-Based on nios II core, to achieve the LCD12864 operation, showing the basic Chinese characters and other characters
can_latest.tar
- CAN controller implimentation using HDL on fpga.SJA1000 chip was taken as refference.
electronic-clock
- 数字电子钟是数字电路中的一个经典学习内容。我们选用电子钟作为最后结课项目的目的，是为了学习verilog语言、FPGA的基本知识、由顶层至底层的设计思路。-VHDL source code for electronic clock design to share
ddc8chou
- 8倍抽取的DDC模块。verilog写的，调试通过-failed to translate