资源列表
my_ip_core
- 在quartusII下用verilog语言自己写的IP核,对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
DE2Project_restored
- 2006nios嵌入式系统电子设计大赛时用过的完整工程。-2006nios Embedded System Electronic Design Competition used when the integrity of the project.
数字边沿鉴相器
- 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
shejiVerilogExample
- Verilog 程序例子 王金明:《Verilog HDL程序设计教程》程序例子,带说明。 -Verilog procedures guo examples : "Verilog HDL Design Guide" procedures example, take note.
clockdesign
- 基于SMART-I实验平台的时钟电路设计与实现,利用vhdl编程进行仿真,并且下载实现,功能正确-based on SMART - I platform clock circuit design and implementation vhdl use simulation program, and download realization function correctly
ModelSim_foundation
- 用实际例子介绍了仿真软件modelsim的基本使用方法,适用于初学者-with practical examples of simulation software modelsim use of the basic method applied to beginners
NAND01GR3B_VH1
- nand flash NAND01GR3B (st)的仿真模型 (VHDL) 的-nand flash NAND01GR3B (st), the simulation model (VHDL)
4bitadd
- 4位全加器原码,包括仿真码和4位计数器码。-four full adder original code, including the simulation code and four counter code.
xuhuanjiucuo
- 循环纠错码译码器VHDL代码。通信方面FPGA设计基础代码。-cycle error correction decoder VHDL code. Communications FPGA design code base.
traffic_control
- 设计制作一个用于十字路口的交通灯控制器 有一组绿、黄、红灯用于指挥交通,绿灯、黄灯和红灯的持续时间分别为20秒、5秒和25秒; 当有特殊情况(如消防车、救护车等)时,两个方向均为红灯亮,计时停止,当特殊情况结束后,控制器恢复原状态,继续正常运行-design a crossroads for the traffic signal controller is a group in green, yellow and red lights to direct traffic. green,
serial_produce
- 设计一个能够自启动的24-1的伪随机码(111101011001000)发生器。 设计一个序列信号发生器,产生一个011100110011序列码。 实现序列1110100。测试序列码波形 个人比较欣赏第二种方法 -to design an 24-1 since the start of the pseudo-random number (111101011001000) generator. Design of a signal sequence generator to pro
multiple_pathanddopple
- 基于多径传输和多普勒频移的 瑞利(Rayleigh)信道的仿真 主要考虑不同条件下的仿真-Based on Multi-Drive transmission and Doppler frequency shift of the Rayleigh (Rayleigh) channel simulation main consideration different The simulation conditions