资源列表
VerilogHDLTestBenchPrimer
- 讲解Verilog 的testbench的书写方法。-on Verilog testbench writing.
USB_I2C_MAC_FPGA_Code
- 《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design
lcdVHDL
- ＶＨＤＬ语言 用来实现对LCD的控制，实现显示功能-VHDL language used to achieve the right LCD control, achieving display function
FSKVHDL
- VHDL语言编写的程序，实现FSK调制与解调及仿真-VHDL prepared by the procedures, FSK modulation and demodulation and Simulation
ADC0809VHDL
- VHDL语言编写的程序，实现控制ADC0809的工作 -VHDL prepared by the procedures, the control Connection between ADC 0809
FIR_beh
- FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.
VHDL_of_example
- 此 为 VHDL 的示例程序,由于最近毕业设计要求使用这个编程,自己收集并整理了一些,供学习使用,希望和大家共同进步,有兴趣的也希望能和我一起讨论交流-this as examples of VHDL procedures, due to the recent graduation design requirements using the program, their collection by some for learning, hope and common progress. Inte
WinFilter08
- WinFilter is a software tool provided as freeware to design digital filter.-WinFilter is a software tool provided as fr eeware to design digital filter.
DES-source-code-by-HDL
- HDL实现的DES算法，及相关的Test bench激励文件-HDL achieve the DES algorithm, and the related documents incentive Test bench
dpll0226
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
DPLL0227+V+qt6
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
pll1218
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.