资源列表
beipin_4
- 自己编写的vhdl语言来实现的四倍频电路,自我感觉还可以,也通过了编译,如果有需要就下载去看看吧-prepared vhdl own language to achieve the four frequency circuit, a sense of self, can also, through a compiler, If there is a need to look at the downloaded Look here
lpm_inv0
- 自己编写的vhdl语言来实现的lpm_inv0电路,自我感觉还可以,也通过了编译,如果有需要就下载去看看吧-prepared vhdl own language to achieve the lpm_inv0 circuit, but also a sense of self, also passed the compiler, if there is a need to look at the downloaded Look here
74138_0
- 这是老师给的3—8译码器的源程序,自己刚才调试过了,真的成功了,哈哈……,有需要就看看吧-This the teacher for the 3-8 decoder source, have their own testing before, and really successful, ha ha ... there is a need to watch it!
4_10_vhdl
- 这是老师给但计数器程序,经过自己刚才调试过了,真的成功了,哈哈……,有需要就看看吧-This the teacher but to counter procedures, testing himself just over a really successful, ha ha ... there is a need to watch it!
VerilogHDLjihe
- 王金明的Verilog HDL程序集合,包含各个常用的程序-guo Verilog HDL procedures set includes all commonly used procedures
I2C_loader
- 用FPGA做主控制器,对IIC从设备配置参数的源程序。Xilinx提供-FPGA master controller, right from the IIC equipment configuration parameters of the source. Xilinx offer
422_to_444
- YUV422转YUV444的FPGA插植算法,由Xilinx提供-YUV422 to YUV444 FPGA implantation algorithm provided by Xilinx
ycrcb_rgb
- YUV转RGB的源程序,使用到了硬件加速器,可利用FGPA的乘法器加速处理速度。-YUV to RGB source, the use of a hardware accelerator, FGPA can be used to speed up the processing speed multiplier.
deinterlace
- Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序,比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
ModelSim_TestBench_VHDL
- ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
N_counter_VHDL
- 任意N进制分频器的标准VHDL代码(原创)-arbitrary N divider 229 standard VHDL code (original)
PulseWidth_detector_VHDL
- 通信控制中常用的脉冲宽度检测程序,VHDL模块化编成实现(原创)-communication control used in pulse width detection procedures, VHDL modular organization to achieve (original)