资源列表
VHDL_pinlvji
- 频率计的VHDL实现，使用10K20，包括顶层电路图，测频范围：1Hz--10MHz-frequency of VHDL, use 10K20, including top-level circuit, measuring frequency range : 1Hz -- 10MHz
EXPT10_2_TENNIS
- 乒乓球游戏电路设计，quartus2平台-game of table tennis circuit design, platform quartus2
EXPT12_5_RSV
- 采用高速A/D的存储示波器设计，quartus2平台-high-speed A / D to the storage oscilloscope design, platform quartus2
EXPT12_10_PHAS
- 数字移相信号发生器设计，采用quartus2平台-digital phase shifting generator design platform using quartus2
vdevice
- 基于FPGA系统的数字电压表设计大范围，超精确的详细报告，共有40多页-FPGA-based system design digital voltage meter large-scale and ultra-precise details of the report, a total of over 40 pages
dianji
- 基于FPGA系统的步进电机控制，内涵详细的源代码-FPGA-based system of stepper motor control, detailed content of the source code! !
pinlvji
- 基于FPGA的数字频率计，超大范围测量，误差非常之小，内含详细程序-FPGA-based digital frequency meter super scope of measurement, the error is very small, containing detailed procedures
blocking
- 基于verilog语言的数据选择器，包括数据选择器的测试模块 -verilog language based on the data selector, including data selection for the test module
memoryverilog
- 一个关于MEMORY设计的原代码,使用VERILOG编写的 希望对大家有些帮助-one of the original Memory design code prepared by the use of verilog we hope to help some
ji
- 这是正玹实现代码,通过LUT来实现的!!!比其他要简单的多!还有方波,三角波的不同的VHDL程序实现. -This is the realization of code are Hsuan Lee, LUT to achieve! ! ! Other than the more simple! There square, triangular wave of the different VHDL program.
half_clk
- 用verilog编写适中分频器 并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
fdivision
- 用verilog编写适中分频器 并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures