资源列表
vhdlcodesss
- i attached the vhdl codings-i attached the vhdl codings..........
hanmingam2
- VHDL语言的（7，4）汉明码译码的设计。-VHDL language (7,4) Hamming code decoding design.
add_tree
- 8*8乘法器 采用树形结构，如有不足之处请指正-8* 8 multiplier with tree structure, please correct me if inadequate
crc16
- Crc校验程序，用于HDLC通信里面和其他的crc校验的代码，是crc16的-Crc verification procedures for the inside and other HDLC communication crc check code is the crc16 of the
parity_chk_32-
- 这是一个用在FPGA上的, VHDL源码, 32位奇偶校验程序.-32 bit parity check
sacdsvcdsvfs
- pong game top level for fpga
mul_addtree
- 用verilog HDL语言实现一个4位的流水线乘法器-Achieve a 4-bit pipelined multiplier using Verilog HDL language
mul24_out48
- 24位数据和24数据相乘得到28位结果。注重面积的优化，采用时钟循环加减的做法。-24-bit data and 24 data obtained by multiplying 28 results. Focus on the area of optimization, the use of the clock cycle subtraction approach.
ARITHMETIC
- 算术乘法器，这是我自己设计的算术乘法器，是用VHDL语言设计的，希望对大家有帮助-Arithmetic multiplier, this is my own design arithmetic multiplier, is designed with VHDL language, and they hope to help everyone
mealy1
- mealy 状态机的独热编码源程序，接受么mealy状态机的编写规则。-mealy state machine of one-hot encoding source code, you mealy state machine to accept the preparation of the rules.
DigitalWatchVerilog
- 一个用Verilog实现的数字跑表的程序 希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help
8-Bit-Up-Counter-With-Load
- 8位计数器，能实现加减计数，经过ise 测试仿真了。符合逻辑-8-bit counter, plus or minus count after ise test simulation. Logical