资源列表
binarycount
- 异步复位、同步置数的四位二进制计数器的VHDL源文件
div16_8
- 用FPGA实现模糊控制器 部分用VHDL语言编写的源程序
viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
OutputManager
- An output manager for Digital Oscilloscope
key_xiaodou
- 本例中用状态机实现了消抖电路： 端口描述：clk 输入检测时钟；reset 复位信号；din 原始按键信号输入； dout 去抖动输出信号。-In this case the state machine used to achieve the elimination shake circuit: Ports Descr iption: clk input test clock reset reset signal din original key signal input dout t
generic_ahb_slave
- Generic AHB Slave for all AHB slave transactions
Program3
- 用 vhdl 语言设计 8 位数码扫描显示电路，显示输出数据直接在程序中给出。增加 8 个 4 位锁存器作为输出显示数据缓冲器，由外部输入8个待显示的十六进制数。-Design with vhdl language display 8-bit digital scanning circuit, display output data are given directly in the program. Increased eight 4-bit latch display data buffer
16mult_signed
- 16*16位的有符号乘法器的verilog语言-16 x 16 signed multiplier verilog language
cordic_fpga
- 基于VHDL的FPGA设计，利用CORDIC IP核设计角度的正余弦算法。-Cosine algorithm VHDL based FPGA designs using CORDIC IP core design angles.
VHDL38decoder
- VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序-38 decoder VHDL language implementation, including program source code file, there are testbench test procedures
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
32_16div
- 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction