资源列表
partiy-generator
- hi this is vhdl code for parity generator/checker
FSK
- FSK 的FPGA实现，使用verilogHDL语言-FSK in FPGA,using verilogHDL
IQ_sin_cos_mod
- Cordic根据输入的IQ正交两路信号求取对应的正切值-Cordic according to input the IQ of orthogonal signal to calculate the corresponding tangent value two road
lcdct
- at070tn83驱动 驱动 驱动 -driver of the lcd
statem
- 元件例化与层次设计，verilog 实例说明-components cases with the level of design, Verilog example
128×16ram
- VHDL程序设计的RAM存储器，双端口，128×16比特
add_ff8
- 利用触发器实现的，8位半加器的VHDL语言实现，适用于altera系列FPGA
PS2
- 设计一个计数器，信号频率为10MHZ，没10M个信号记一次数。-counter
1addto10
- 本程序是一个从1累加到10的小算法，用VHDL编写与实现-no
spi25
- 铁电SPI 读写 FPG 外挂SPI铁电存储器的读写控制代码.-FM25** SPI R/W
AD9957_Signal_Generate
- AD9957芯片通过FPGA配置的verilog程序,要自建工程，代码测试完全可用-AD9957 chip FPGA configuration verilog program, to be self-built project, code test is completely available
rxtx
- 串行通信程序，程序稳定可靠，分为好多模块代码写的不错，值得参考，-Serial communication program, the program is reliable, divided into a lot of module code written well worth considering.