资源列表
cic5r61
- 实现CIC5级滤波器功能。可以达到提亲一位或者延迟一采样的功能-Achieve CIC5 stage filter function.
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog
msk_top
- msk的verilog程序 利用ＦＰＧＡ实现
ad_in
- 用于FPGA,数据宽度转换。10位数据输入，经转换后128位输出模块。-For the FPGA, the data width conversion. 10-bit data input, the converted output module 128.
fifomodule
- 定义了一个FIFO和相关的读写功能,比较实用,可直接作为模块使用-define a FIFO that contains the relative read and write functions, and it can be used as module directly in ISE.
FIFO
- common FIFO module and it is easy to involve in ur design.
mlt
- --a0 a1 的输入我们用 k1 k2 代替 --b0 b1 的输入我们用 k3 k4 代替 --一开始数码管显示的是9.应为(11)*(11)就等于9 --数码管显示相减结?-- A0 a1 input we use the k1 k2 instead- b0 b1 input with k3 k4 instead- a digital display is 9. (11)* (11) is equivalent to 9- digital display subtract
shaomiaoqudongxianshidianlu
- 为了减少8位显示信号的接口连接线，实验箱中的数码显示采用扫描 显示工作模式。即8位数码管的七段译码输入（a,b,c,d,e,f,g）是并联在 一起的，而每一个数码管是通过一个3位选择sel[2..0]来选定 的。-In order to reduce the 8-bit display signal interface cable, digital display in the experimental box scan display mode of operation. I.e. the s
3to8decoder
- 3 to 8 decoder is used to decode from 3 bit data to 8 bit data used in many applications
spimaster
- 一般AD的spi配置代码，考虑的采样的时序问题。-General AD, spi configuration code, consider a sampling of the timing problems.
invsinwave
- vhdl code for inverse sine wave.
LANE0REGISTER
- The purpose of the Lane register is to get the TLPs or DLLPs from the Byte Striping Logic and to store the obtained data in the internal registers and then send the data to the scrambler and then get the Bit-by-Bit scrambled data from the Scrambler a