资源列表
complete
- 对输入的8位二进制数求其补码运算，或是由补码求源码-get the complete data
FIFO
- 先入先出队列(First Input First Output，FIFO)这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。-FIFO queue (First Input First Output, FIFO) which is a traditional sequential execution method, first enter the command to finish and retire, only to follow the implementatio
randomization
- m序列码生成文件-M code generation file................
DSP_EMIF_if
- fpga的emif的设计与开发的源代码-source code the fpga emif, design and development! ! ! !
SCAN-vhdl
- maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program
lsd
- 以上是VHDL硬件描述语言写的一个简单锝路流水灯程序,希望对刚接触VHDL的朋友有一定帮助-These are the VHDL hardware descr iption language written in a simple flow path lights technetium procedures,刚接触VHDL want to have some friends to help
unidadcontrol
- Para la unidad de control del algoritmo SHA
traffic-light
- keil上运行，用单片机实现的十字路口交通灯功能，功能实用-keil to run on the MCU crossroads traffic lights function, functional
add_ff8cin
- 触发器实现的，8位全加器的VHDL语言实现，适用于altera系列的FPGA
AdControl
- AD7470_7472 采样的verilog 代码，通过硬件调试直接可用的，程序里 定义了100个8位存储器，用于接收采样的数据，当100个数据接收完毕时不在接收 ，并一直开始循环输出 所采数据。用时 修改下就行-FPGA code for analogue and digital conversion,which has been tested with hardware.
FSMwithOutputsDecode
- 有限状态机FSM with Outputs Decoded in Parallel Output Register-FSM with Outputs Decoded in Parallel Output Register
FP-AND-DIPLAY
- VHDL分频程序：将输入为MHz数量级的频率进行分频，得到自己所需的Hz数量级频率。 七段数码管显示程序：将输出进行译码，通过数码管显示。-VHDL divider, divide the input MHz frequency of the order of magnitude, to get the required Hz magnitude frequency. Segment digital tube display program: the output of decoding