资源列表
qpsk
- QKSK 调制 解调 调试成功 -QKSK modem debugging success
16-bit-A-DCa16-bit-DAC-VHDL
- 16-bit Analogue to Digital Converter&16-bit Digital to Analogue Converter VHDL source code.在modelsim下仿真通过-16-bit Analogue to Digital Converter & 16-bit Digital to Analogue Converter VHDL source code. Simulated in modelsim
youxianpaidui
- CPLD/FPGA开发常用程序，用CPLD实现可编程逻辑电路，优先排队电路编程实现-CPLD/FPGA development of common procedures, with CPLD programmable logic circuit, priority queuing circuit programming
用VHDL生成伪随机数
- 用VHDL生成伪随机数，资源占用少，最高频率可达200MHz
VHDL
- 8位相等比较器含源代码，用VHDL语言编写，具体很高的实用性，供读者参考-8, phase comparator, such as with the source code, using VHDL language, the specific relevance of a high for the reader is referred to
automachine
- 自动售货机的状态机实现 自动售货机的状态机实现-this is a automachine
div_clk_encoder
- 对系统时候进行任意的偶数分频，只要修改几个位置即可，方便移植。另一个是7段数码管驱动程序。使用-System when any even divide, as long as the modified several locations can be easily ported.
p_s_fpga_to_mcu
- fpga与单片机通信，fpga端，fpga发送，单片机接受，能发多位数据，可以自己设置-Communication with the microcontroller fpga, fpga end, fpga sent microcontroller to accept, to send a number of data, you can set up their own
chenxu
- 序列检测其设计，检测11100110。并通过七段显示译码器显示。- Sequence Detection its design, testing 11100110.And through the seven-segment display decoder display.
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
counter
- 基于VHDL的计数代码，可用于FPGA芯片对步进电机的控制-Count based on VHDL code for FPGA chips can be used to control stepper motor
seg70
- 用VHDL写的7段LED循环显示，8根Data，8根Cotl，经过实际的板子验证。-Written with VHDL 7 segment LED display cycle, 8 Data, 8 根 Cotl, after the actual board certification.