资源列表
DivFreq
- diviseur de frequence en VHDL
jiaotongdeng)
- 交通灯 VHDL源码 功能实现 外网摘写-VHDL source function realization of traffic lights outside the network Zhai write
echo
- 硬件描述语言 veilog 回声效果实验-Hardware descr iption language veilog echo effect experiment
clock
- 本实验实现一个能显示小时，分钟，秒的数字时钟。-The experimental realization of a can display hours, minutes, seconds, the digital clock.
pwm
- 基于FPGA的PWM波的产生，通过计数的方法实现-FPGA-based generation of PWM wave
shuzipaobiao
- 设计一个数字跑表，该跑表具有复位，暂停，秒表计时功能，暂停后恢复时，在原来数值基础上继续计数-Design a digital stopwatch, the stopwatch has reset, pause, stop watch timing function, recovery after a pause, continue on the basis of the original value of count
adder
- 用两个方法实现2位全加器，没有错误，仅供参考。-Can realize two eight bits of Numbers is equal, no error, for reference. With two method two QuanJia device without any error, only supplies the reference.
horse_light
- verilog语言设计跑马灯程序 同步电路设计方式 经fpga验证-Verilog language design marquee program the synchronous circuit design fpga verification
code1-
- SPI recever avr programing
infrared_carrier
- 红外载波的发送模块，可以用于载波产生，设计很简单，容易看懂。-IR carrier transmission module can be used for carrier generation, the design is very simple, easy to understand.
clockdiv
- Clock division implementation on verilog VHDL
median5x1
- 一个自己写的5x1中值滤波算法，可以直接使用.-It is 5x1 median filter arithmetic.