资源列表
m_sequence_mod
- 伪随机序列，m序列发生器，可灵活配置抽头文件，已经仿真通过-m SEQ MODULE
QAM-16-OFDM_Module
- QAM16-verilog code for OFDM module. includes mapping design
crccode
- CRC循环冗余检验 Verilog 编码程序
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
12
- hdb3编码的 hdb3编码的-HDB3 coding HDB3 encoding
statemachine
- RTL级verilog代码 用状态机实现 将输入数据写入16位寄存器，输出其除以7所得的余数（4位）-RTL-lever verilog code Using FSM to realize the following function:input the data into a 16bit register, divide it by 7, and output the 4-bit remainder
pll
- verilog硬件描述语言实现数字锁相环功能仿真,-Digital phase-locked loop using verilog
CORDIC
- 基于FPGA的CORDIC数字计算机的设计-CORDIC FPGA-based design of digital computers
password-locker
- 简单的单号密码锁程序 在verilog上实现 包括测试程序-simple password locker programme based on verilog, which including test bench
4
- 8x9FIFO逻辑功能的VHDL语言程序，程序中定义了四个进程，用来寄存数据，控制读指针，控制写指针以及控制三态输出-VHDL language program for 8x9FIFO logic function, the program defines four processes for data storage to control the read pointer to control the write pointer as well as to control three-stat
WERDTEST
- CCD DRIVER 本软件用于线性CCD 传感器时序控制 -CCD DRIVER software for the linear CCD sensor timing control
基于 FPGA 实现的冒泡排序法范例
- 基于 FPGA 实现的冒泡排序法范例,Verilog 的语法.