资源列表
mux32b2a1
- 32 bits Multiplexor 2x1-32 bits Multiplexor 2x1
cpu
- using vhdl design cpu
uart
- 串口试验的Verilog描述，比较详细的解释，值得初学者学习-UART of Verilog
ha
- half adder fully structural
adder_tp
- 本代码包含四位全加器和四位全加器的测试平台。-The code contains four full adders and four full adder test platform.
decode_display
- 基于FPGA的动态数码管驱动程序，用verilog HDL语言实现。-FPGA-based digital control of dynamic drivers, using verilog HDL language.
fir
- 用状态机编写的FIR，verilog代码，已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
register
- vhdl code for register and detemines how register works -vhdl code for register and detemines how register works
DigitalEggTimer
- timeer for cooks with simulation
fuyongqi
- vhdl实现解复用器的功能，16位，高效移植性好-vhdl implementation demultiplexer function 16-bit, high efficiency and good graft
fsm_tb
- An odd parity checker as an FSM using VHDL
mul
- multiplier in verilog