资源列表
simple-divider
- simple divider vhdl code
38yima
- 用VHDL语言实现38译码器译码功能并用数码管显示-38 Decoder decoding functions with digital display
321
- VHDL模为10，范围为0-9，可变模计数器是指计数／模值可根据需要进行变化的计数器。-VHDL model of 10, the range of 0-9, the variable modulus counter is counting/A value can be changed as needed counter.
state_machine
- 简单的状态机，有8个状态,数码管输出当前状态的编号 state0--state1--state2--state3--state4--state5--state6-state7--state0-Simple state machine with 8 states, the digital output of the current state of the number state0- state1- state2- state3- state4- state5- state6-state7
onescount
- code to reduce memory
yimaqi
- 这是一个译码器，与编码器功能相反，可以用于设计抢答器等，便于在实验箱上演示-This is a decoder, and encoder On the contrary, can be used to design Responder so easy to be demonstrated in the experimental box
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
ncr
- module to wait 2 clocks for SD card
alu
- 实现五位加法器功能，还有ALU的程序模块！同时有四位全加器的功能模块！-Adder to achieve five functions, as well as program modules ALU! At the same time there are four full-adder modules!
and4
- used for logical and-ing two 1-bit numbers
alu
- 一个简单的四位alu，用max+plusII运行-a simple 4bit alu by vhdl.You can use max+plusII to text it
MIF_file_of_Sine_Wave_Generator
- 在Quartus的DDS设计中，通常会用到mif或者hex文件存储函数值，被ROM的IP模块调用。本程序是在Matlab环境下，根据所需数据位数和长度自定义mif文件。-Quartus DDS design, usually used in the mif or hex file storage function value, call the ROM of IP modules. This program is in the Matlab environment, according to t