资源列表
piso.txt
- PISO implemented in VHDL.
rom_led_8
- 气短数码管的另一种驱动形式，采取代码较少。-Shortness of breath, another drive digital form
COUNTER.ZIP
- 4 bit counter example for CHDL beginners
lagrange
- 对原信号进行拉格朗日插值运算，实现信号重采样-The original signal Lagrange interpolation operation, to achieve signal resampling
code
- 通过对VGA 接口的显示控制设计，理解VGA 接口的时序工作原理，掌握通过计数器产 生时序控制信号的方法以及用MEGEFUNCTION 制作锁相环的方法。-Through the VGA display control interface design, understanding the timing works VGA interface, timing control method of generating control signals produced by the count
infrastructure.vhd
- infrastructure block for analog loop, vhdl, fpga, de2
D_flipflop
- D flip flop source and test bench verilog code 6
AD0809
- 基于FPGA的AD/DA控制VHDL程序-Based on the FPGA AD/DA control VHDL program
tcm_enc
- 这是一个用VERILOG HDL 编写的TCM信道编码-This is a VERILOG HDL prepared with TCM channel coding
alu
- arithmetical-logic unit design in Verilog
111
- 用vhdl实现按键消抖 和 用vhdl写pwm-Vhdl implementation with shaking and the use of key consumer written pwm vhdl
s_to_p
- serial to paralle a vhdl code