资源列表
add4
- 加法器的verilog代码，描述一个四位的加法器，可移植性很强，适合很多场合。-The adder verilog code, describe a four of the adder, portability is very strong, suitable for many occasions.
Keyboard
- 4×4键盘 描述了基本键盘功能，利于新手进行编程-4×4 keyboard
KEY_LED
- 一个入门级的程序，按键点亮led的程序！初学可以下载下来参考~-light led
sram_bridge
- 多用户访问SRAM，使用开关切换，包括数据总线和控制信号，fpga总线桥-Multi-user access to SRAM, switching, and includes a data bus and control signal, FPGA bus bridge
FIFO_control
- 一个32*8FIFO控制器代码，涉及输入输出时的地址变化及参数应用。-A 32* 8FIFO controller code, involving the input and output address changes and parameter applications.
dds-design
- fpga实现dds，实现任意波形输出信，设计代码verilog-dds fpga realization
A-Two-bits-Counter-Using-VHDL
- 两位VHDL编译计数器的简单实现，并带有异步的复位功能。-A Brief Realization of Two-bits Counter, with an Asynchronous Reset Function
taxi
- 出租车计价器源码 module distancemokuai-Taximeter source module distancemokuai
huanxingfenpeiqi
- 步进电机的环形分配器，VHDL文件源码，经编译全通过，没有仿真，-Annular distributor of the stepper motor, VHDL file source, compile the whole through, there is no simulation.
cnt4
- 4位2进制计数器，可以灵活组装成任意位数的2进制计数器-4 binary counter, can be flexibly assembled into arbitrary digit binary counter
fenpinqi.rar
- 用VHDL语言设计分频器要求是将128赫兹的脉冲信号经过分频器分别产生64赫兹，32赫兹，16赫兹，8赫兹，4赫兹, 2赫兹，1赫兹，0.5赫兹的8种频率的信号,Divider design using VHDL language requirement will be 128 Hz pulses were generated through divider 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz, 0.5 Hz frequency of the
test
- PIC18F452的1602LCD显示程序，经过本人验证-Display program the PIC18F452 1602LCD